The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2012

Filed:

Oct. 10, 2008
Applicants:

Karen Aleksanyan, Yerevan, AM;

Karen Amirkhanyan, Yerevan, AM;

Sergey Karapetyan, Yerevan, AM;

Alexander Shubat, Los Altos Hills, CA (US);

Samvel Shoukourian, Yerevan, AM;

Valery Vardanian, Yerevan, AM;

Yervant Zorian, Santa Clara, CA (US);

Inventors:

Karen Aleksanyan, Yerevan, AM;

Karen Amirkhanyan, Yerevan, AM;

Sergey Karapetyan, Yerevan, AM;

Alexander Shubat, Los Altos Hills, CA (US);

Samvel Shoukourian, Yerevan, AM;

Valery Vardanian, Yerevan, AM;

Yervant Zorian, Santa Clara, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler.


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