The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2012

Filed:

Oct. 08, 2009
Applicants:

Hyun-soo Chung, Hwaseong-si, KR;

Seung-duk Baek, Yongin-si, KR;

Dong-ho Lee, Seongnam-si, KR;

Dong-hyeon Jang, Suwon-si, KR;

Seong-deok Hwang, Seoul, KR;

Inventors:

Hyun-Soo Chung, Hwaseong-si, KR;

Seung-Duk Baek, Yongin-si, KR;

Dong-Ho Lee, Seongnam-si, KR;

Dong-Hyeon Jang, Suwon-si, KR;

Seong-Deok Hwang, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.


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