The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2012
Filed:
Oct. 22, 2009
Wagdi W. Abadeer, Essex Junction, VT (US);
Lilian Kamal, Legal Representative, Saratoga, CA (US);
Kiran V. Chatty, Essex Junction, VT (US);
Jason E. Cummings, Albany, NY (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Robert J. Gauthier, Essex Junction, VT (US);
Jed H. Rankin, Jr., Essex Junction, VT (US);
Robert R. Robison, Essex Junction, VT (US);
William R. Tonti, Essex Junction, VT (US);
Wagdi W. Abadeer, Essex Junction, VT (US);
Lilian Kamal, legal representative, Saratoga, CA (US);
Kiran V. Chatty, Essex Junction, VT (US);
Jason E. Cummings, Albany, NY (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Robert J. Gauthier, Essex Junction, VT (US);
Jed H. Rankin, Jr., Essex Junction, VT (US);
Robert R. Robison, Essex Junction, VT (US);
William R. Tonti, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.