The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

Jul. 30, 2008
Applicants:

Jonathan K. Abrokwah, Chandler, AZ (US);

Ravindranath Droopad, Chandler, AZ (US);

Matthias Passlack, Chandler, AZ (US);

Inventors:

Jonathan K. Abrokwah, Chandler, AZ (US);

Ravindranath Droopad, Chandler, AZ (US);

Matthias Passlack, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

An improved insulated gate field effect device () is obtained by providing a substrate () desirably comprising a III-V semiconductor, having a further semiconductor layer () on the substrate () adapted to contain the channel () of the device () between spaced apart source-drain electrodes () formed on the semiconductor layer (). A dielectric layer () is formed on the semiconductor layer (). A sealing layer () is formed on the dielectric layer () and exposed to an oxygen plasma (). A gate electrode () is formed on the dielectric layer () between the source-drain electrodes (). The dielectric layer () preferably comprises gallium-oxide () and/or gadolinium-gallium oxide (), and the oxygen plasma () is preferably an inductively coupled plasma. A further sealing layer () of, for example, silicon nitride is desirably provided above the sealing layer (). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.


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