The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

Jun. 28, 2004
Applicants:

Takashi Noma, Ota, JP;

Hiroyuki Shinogi, Ora-gun, JP;

Nobuyuki Takai, Osato-gun, JP;

Katsuhiko Kitagawa, Ora-gun, JP;

Ryoji Tokushige, Ora-gun, JP;

Takayasu Otagaki, Hashima, JP;

Tatsuya Ando, Hashima, JP;

Mitsuru Okigawa, Nagoya, JP;

Inventors:

Takashi Noma, Ota, JP;

Hiroyuki Shinogi, Ora-gun, JP;

Nobuyuki Takai, Osato-gun, JP;

Katsuhiko Kitagawa, Ora-gun, JP;

Ryoji Tokushige, Ora-gun, JP;

Takayasu Otagaki, Hashima, JP;

Tatsuya Ando, Hashima, JP;

Mitsuru Okigawa, Nagoya, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.


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