The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

Jan. 31, 2008
Applicants:

Vinod Kariat, Sunnyvale, CA (US);

Igor Keller, Pleasanton, CA (US);

Eddy Pramono, Santa Clara, CA (US);

Inventors:

Vinod Kariat, Sunnyvale, CA (US);

Igor Keller, Pleasanton, CA (US);

Eddy Pramono, Santa Clara, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit ('IC') layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.


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