The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

Jan. 13, 2011
Applicants:

Tae Sung Jeong, Ichon-si, KR;

Hyeog Chan Kwon, Seoul, KR;

Youngcheol Kim, Youngin-si, KR;

Inventors:

Tae Sung Jeong, Ichon-si, KR;

Hyeog Chan Kwon, Seoul, KR;

Youngcheol Kim, Youngin-si, KR;

Assignee:

Stats Chippac Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 21/98 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.


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