The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

Nov. 12, 2010
Applicants:

Seok-hoon Kim, Hwaseong-si, KR;

Chung-geun Koh, Seoul, KR;

Kwan-yong Lim, Seongnam-si, KR;

Hyun-jung Lee, Suwon-si, KR;

Tae-ouk Kwon, Hwaseong-si, KR;

Sang-bom Kang, Seoul, KR;

Inventors:

Seok-Hoon Kim, Hwaseong-si, KR;

Chung-Geun Koh, Seoul, KR;

Kwan-Yong Lim, Seongnam-si, KR;

Hyun-Jung Lee, Suwon-si, KR;

Tae-Ouk Kwon, Hwaseong-si, KR;

Sang-Bom Kang, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.


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