The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2012
Filed:
Jul. 02, 2008
Jindrich Zejda, Sunnyvale, CA (US);
Narender Hanchate, Sunnyvale, CA (US);
Rupesh Nayak, San Ramon, CA (US);
LI Ding, San Jose, CA (US);
Jindrich Zejda, Sunnyvale, CA (US);
Narender Hanchate, Sunnyvale, CA (US);
Rupesh Nayak, San Ramon, CA (US);
Li Ding, San Jose, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.