The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Sep. 28, 2005
Hidefumi Takaya, Nishikamo-gun, JP;
Kimimori Hamada, Toyota, JP;
Kyosuke Miyagi, Nishikamo-gun, JP;
Yasushi Okura, Toyokawa, JP;
Akira Kuroyanagi, Okazaki, JP;
Norihito Tokura, Okazaki, JP;
Hidefumi Takaya, Nishikamo-gun, JP;
Kimimori Hamada, Toyota, JP;
Kyosuke Miyagi, Nishikamo-gun, JP;
Yasushi Okura, Toyokawa, JP;
Akira Kuroyanagi, Okazaki, JP;
Norihito Tokura, Okazaki, JP;
Toyota Jidosha Kabushiki Kaisha, Toyota-shi, JP;
Denso Corporation, Kariya-shi, JP;
Abstract
The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.