Flat semiconductor package with half package molding

Abstract

In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads, the exposed portions of the bottom surfaces of which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of both rows thereof being exposed in a common exterior surface of the package body. In certain embodiments of the present invention, the top surfaces of at least some of leads of the leadframe are also exposed in an exterior surface of the package body.