The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2011
Filed:
Nov. 13, 2009
Chih-ping Lin, Taipei County, TW;
Shih-ming Chen, Hsinchu, TW;
Hsiao-ying Yang, Hsinchu, TW;
Wen-hsien Liu, Taoyuan County, TW;
Po-sheng HU, Taipei County, TW;
Chih-Ping Lin, Taipei County, TW;
Shih-Ming Chen, Hsinchu, TW;
Hsiao-Ying Yang, Hsinchu, TW;
Wen-Hsien Liu, Taoyuan County, TW;
Po-Sheng Hu, Taipei County, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.