The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Jan. 29, 2009
Rohit Kapur, Cupertino, CA (US);
Anshuman Chandra, Mountain View, CA (US);
Yasunari Kanzawa, Sunnyvale, CA (US);
Jyotirmoy Saikia, Bangalore, IN;
Rohit Kapur, Cupertino, CA (US);
Anshuman Chandra, Mountain View, CA (US);
Yasunari Kanzawa, Sunnyvale, CA (US);
Jyotirmoy Saikia, Bangalore, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.