The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2011

Filed:

Jul. 15, 2008
Applicants:

Robert D. Herzl, South Burlington, VT (US);

Robert S. Horton, Colchester, VT (US);

Kenneth A. Lauricella, Colchester, VT (US);

David W. Milton, Underhill, VT (US);

Clarence R. Ogilvie, Huntington, VT (US);

Paul M. Schanely, Essex Junction, VT (US);

Nitin Sharma, South Burlington, VT (US);

Tad J. Wilder, South Hero, VT (US);

Charles B. Winn, Colchester, VT (US);

Inventors:

Robert D. Herzl, South Burlington, VT (US);

Robert S. Horton, Colchester, VT (US);

Kenneth A. Lauricella, Colchester, VT (US);

David W. Milton, Underhill, VT (US);

Clarence R. Ogilvie, Huntington, VT (US);

Paul M. Schanely, Essex Junction, VT (US);

Nitin Sharma, South Burlington, VT (US);

Tad J. Wilder, South Hero, VT (US);

Charles B. Winn, Colchester, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.


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