The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8055486 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 08, 2011

Filed:

Aug. 06, 2008
Applicants:

Daniel Douriet, Round Rock, TX (US);

Anand Haridass, Austin, TX (US);

Andreas Huber, Austin, TX (US);

Colm B. O'reilly, Austin, TX (US);

Bao Gia-harvey Truong, Austin, TX (US);

Roger D. Weekly, Austin, TX (US);

Inventors:

Daniel Douriet, Round Rock, TX (US);

Anand Haridass, Austin, TX (US);

Andreas Huber, Austin, TX (US);

Colm B. O'Reilly, Austin, TX (US);

Bao Gia-Harvey Truong, Austin, TX (US);

Roger D. Weekly, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.


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