The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Mar. 20, 2008
Applicant:

Kee W. Park, San Jose, CA (US);

Inventor:

Kee W. Park, San Jose, CA (US);

Assignee:

NetLogic Microsystems, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus are disclosed for improving reliability in a memory circuit. The method includes coupling a pull-down element to a word line, the pull-down element coupled distal to a word line driver. The method further includes, when the word line exhibits a defect causing a first portion of the word line to be electrically isolated from a second portion of the word line, holding the second portion of the word line at a logically low value using the pull-down element. A memory device is disclosed that includes a word line coupled to a memory cell, a word line driver coupled to one end of the word line, and a pull-down element coupled proximate the other end of the word line. The pull-down element is operable, when the word line exhibits a defect causing a first portion of the word line to be electrically isolated from a second portion of the word line, to hold the second portion of the word line at a logical low value.


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