The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Jan. 26, 2009
Applicants:

Thomas W. Mountsier, San Jose, CA (US);

Roey Shaviv, Palo Alto, CA (US);

Steven T. Mayer, Lake Oswego, OR (US);

Ronald A. Powell, Portola Valley, CA (US);

Inventors:

Thomas W. Mountsier, San Jose, CA (US);

Roey Shaviv, Palo Alto, CA (US);

Steven T. Mayer, Lake Oswego, OR (US);

Ronald A. Powell, Portola Valley, CA (US);

Assignee:

Novellus Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.


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