The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2011
Filed:
Oct. 01, 2008
Wayne French, San Jose, CA (US);
Pragati Kumar, Santa Clara, CA (US);
Prashant Phatak, San Jose, CA (US);
Tony Chiang, Campbell, CA (US);
Wayne French, San Jose, CA (US);
Pragati Kumar, Santa Clara, CA (US);
Prashant Phatak, San Jose, CA (US);
Tony Chiang, Campbell, CA (US);
Intermolecular, Inc., San Jose, CA (US);
Abstract
This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or 'off' current characteristics (Ior I, respectively) or a maximum ratio of 'on' current to “off” current (I/I).