The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2011
Filed:
Dec. 04, 2008
Kenneth Allen Honer, Santa Clara, CA (US);
Belgacem Haba, Saratoga, CA (US);
David Ovrutsky, Charlotte, NC (US);
Charles Rosenstein, Ramat Beit Shemesh, IL;
Guilian Gao, San Jose, CA (US);
Kenneth Allen Honer, Santa Clara, CA (US);
Belgacem Haba, Saratoga, CA (US);
David Ovrutsky, Charlotte, NC (US);
Charles Rosenstein, Ramat Beit Shemesh, IL;
Guilian Gao, San Jose, CA (US);
Tessera, Inc., San Jose, CA (US);
Abstract
A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.