The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Feb. 25, 2009
Won Gi Min, Chandler, AZ (US);
Geoffrey W. Perkins, Chandler, AZ (US);
Kyle D. Zukowski, Scottsdale, AZ (US);
Jiang-kai Zuo, Chandler, AZ (US);
Won Gi Min, Chandler, AZ (US);
Geoffrey W. Perkins, Chandler, AZ (US);
Kyle D. Zukowski, Scottsdale, AZ (US);
Jiang-Kai Zuo, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An antifuse (') comprises, first () and second (′) conductive regions having spaced-apart curved portions (), with a first dielectric region () therebetween, forming in combination with the curved portions () a curved breakdown region () adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region () is desirably provided adjacent the breakdown region () to inhibit heat loss from the breakdown region () during programming. Lower programming voltages and currents are observed compared to antifuses () using substantially planar dielectric regions (). In a further embodiment, a resistive region () is inserted in one lead (′) of the antifuses (′) with either planar () or curved () breakdown regions to improve post-programming sense reliability.