The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
Sep. 19, 2008
Fujio Masuoka, Chuo-ku, JP;
Hiroki Nakamura, Chuo-ku, JP;
Fujio Masuoka, Chuo-ku, JP;
Hiroki Nakamura, Chuo-ku, JP;
Unisantis Electronics (Japan) Ltd., Tokyo, JP;
Tohoku University, Miyagi, JP;
Abstract
There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters are coupled with each other, each of the n inverters has: a pMOS SGT; an nMOS SGT, an input terminal arranged so as to connect a gate of the pMOS SGT with a gate of the nMOS SGT; an output terminal arranged to connect a drain diffusion layer of the pMOS SGT with a drain diffusion layer of the nMOS SGT in an island-shaped semiconductor lower layer; a pMOS SGT power supply wiring line arranged on a source diffusion layer of the pMOS SGT; and an nMOS SGT power supply wiring line arranged on a source diffusion layer of the NMOS SGT, and an n−1th output terminal is connected with an nth input terminal.