The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2011
Filed:
Jun. 24, 2008
Nobuyuki Ikeguchi, Suwon-si, KR;
Keungjin Sohn, Seoul, KR;
Joonsik Shin, Suwon-si, KR;
Jung-hwan Park, Seongnam-si, KR;
Nobuyuki Ikeguchi, Suwon-si, KR;
Keungjin Sohn, Seoul, KR;
JoonSik Shin, Suwon-si, KR;
Jung-Hwan Park, Seongnam-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.