The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2011
Filed:
Oct. 31, 2007
Peilin Wang, Beijing, CN;
Edouard D. DE Frésart, Tempe, AZ (US);
Ganming Qin, Chandler, AZ (US);
Hongwei Zhou, Beijing, CN;
Peilin Wang, Beijing, CN;
Edouard D. de Frésart, Tempe, AZ (US);
Ganming Qin, Chandler, AZ (US);
Hongwei Zhou, Beijing, CN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A TMOS device () is formed using a semiconductor layer () of a first type. First and second regions () of the second type are formed in the semiconductor layer and are spaced apart. A third region () is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack () is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions () of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.