The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2011
Filed:
Jul. 10, 2006
You Chye How, Melaka Tengah, MY;
Shee Min Yeong, Melaka Tengah, MY;
Peng Soon Lim, Melaka Tengah, MY;
Sek Hoi Chong, Melaka Tengah, MY;
You Chye How, Melaka Tengah, MY;
Shee Min Yeong, Melaka Tengah, MY;
Peng Soon Lim, Melaka Tengah, MY;
Sek Hoi Chong, Melaka Tengah, MY;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.