The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2011

Filed:

Oct. 31, 2008
Applicants:

Jung-sheng Hoei, Newark, CA (US);

Jonathan Pabustan, San Lorenzo, CA (US);

Vishal Sarin, Cupertino, CA (US);

William H. Radke, Los Gatos, CA (US);

Frankie F. Roohparvar, Monte Sereno, CA (US);

Inventors:

Jung-Sheng Hoei, Newark, CA (US);

Jonathan Pabustan, San Lorenzo, CA (US);

Vishal Sarin, Cupertino, CA (US);

William H. Radke, Los Gatos, CA (US);

Frankie F. Roohparvar, Monte Sereno, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.


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