Dynamic memory word line driver scheme

Abstract

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vand V, and for providing a select signal at levels Vand V, a high voltage supply source Vwhich is higher in voltage than V, a circuit for translating the select signals at levels Vand Vto levels Vand Vand for applying it directly to the word lines whereby an above Vvoltage level word line is achieved without the use of double boot-strap circuits.