The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2011

Filed:

Feb. 22, 2008
Applicants:

Michael W. Dotson, Binghamton, NY (US);

Anthony Degroff Drumm, Rochester, MN (US);

Dazhuang J. MA, White Plains, NY (US);

Ruchir Puri, Baldwin Place, NY (US);

Louise H. Trevillyan, Katonah, NY (US);

Inventors:

Michael W. Dotson, Binghamton, NY (US);

Anthony DeGroff Drumm, Rochester, MN (US);

Dazhuang J. Ma, White Plains, NY (US);

Ruchir Puri, Baldwin Place, NY (US);

Louise H. Trevillyan, Katonah, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.


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