The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2011
Filed:
Apr. 12, 2008
Rajit Chandra, Cupertino, CA (US);
Paolo Carnevali, San Jose, CA (US);
John Yanjiang Shu, Livermore, CA (US);
Adi Srinivasan, Fremont, CA (US);
Rajit Chandra, Cupertino, CA (US);
Paolo Carnevali, San Jose, CA (US);
John Yanjiang Shu, Livermore, CA (US);
Adi Srinivasan, Fremont, CA (US);
Gradient Design Automation Inc., Santa Clara, CA (US);
Abstract
Transient thermal simulation of semiconductor chips uses region-wise variable spatial grids and variable temporal intervals, enabling spatio-temporal thermal analysis of semiconductor chips. Temperature rates of change across a die and/or package of an integrated circuit are computed and tracked versus time. Critical time interval(s) for temperature evaluation are determined. Temperatures of elements, components, devices, and interconnects are updated based on a 3D full chip temperature analysis. Respective power dissipations are updated, as a function of the temperatures, with an automated interface to one or more circuit simulation tools. Subsequently new temperatures are determined as a function of the power dissipations. User definable control and observation parameters enable flexible and efficient transient thermal analysis. The parameters relate to power sources, monitoring, reporting, error tolerances, and output snapshots. Viewing of waveform plots and 3D spatial variations of temperature enable efficient communication of results of the thermal analysis with designers of integrated circuits.