The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2011

Filed:

Apr. 04, 2008
Applicants:

Huang Liu, Singapore, SG;

Jeff Shu, Singapore, SG;

Luona Goh, Singapore, SG;

Wei LU, Singapore, SG;

Inventors:

Huang Liu, Singapore, SG;

Jeff Shu, Singapore, SG;

Luona Goh, Singapore, SG;

Wei Lu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed OTEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the OTEOS oxide.


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