The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Sep. 28, 2006
Kuo-chyuan Tzeng, Hsinchu, TW;
Jian-yu Shen, Yunlin, TW;
Kuo-chi Tu, Hsinchu, TW;
Kuo-ching Huang, Hsinchu, TW;
Chin-yang Chang, Hsinchu, TW;
Kuo-Chyuan Tzeng, Hsinchu, TW;
Jian-Yu Shen, Yunlin, TW;
Kuo-Chi Tu, Hsinchu, TW;
Kuo-Ching Huang, Hsinchu, TW;
Chin-Yang Chang, Hsinchu, TW;
Taiwan Semiconductor Manufacuturing Co., Ltd., Hsin-Chu, TW;
Abstract
Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.