The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Feb. 03, 2009
Choongryul Ryou, Seongnam-si, KR;
Seunghwan Lee, Fishkill, NY (US);
Jun Yuan, Fishkill, NY (US);
Victor Chan, Newburgh, NY (US);
Manfred Eller, Beacon, NY (US);
Nam Sung Kim, Beacon, NY (US);
Narasimhulu Kanike, Wappingers Falls, NY (US);
Srikanth Balaji Samavedam, Fishkill, NY (US);
Choongryul Ryou, Seongnam-si, KR;
Seunghwan Lee, Fishkill, NY (US);
Jun Yuan, Fishkill, NY (US);
Victor Chan, Newburgh, NY (US);
Manfred Eller, Beacon, NY (US);
Nam Sung Kim, Beacon, NY (US);
Narasimhulu Kanike, Wappingers Falls, NY (US);
Srikanth Balaji Samavedam, Fishkill, NY (US);
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
Generating an embedded resistor in a semiconductor device includes forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed above the STI region; etching the silicon layer to yield a polyconductor above the STI region; oxidizing the polyconductor; depositing an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer above the STI region; patterning a transistor gate with a photo-resist mask on another portion of the silicon layer away from the STI region; and etching the silicon layer to yield a transistor structure away from the STI region and a resistor structure above the STI region.