The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2011

Filed:

Aug. 04, 2008
Applicants:

Yusuke Kawaguchi, Kanagawa-ken, JP;

Kazuya Nakayama, Kanagawa-ken, JP;

Tsuyoshi Ohta, Kanagawa-ken, JP;

Takeshi Uchihara, Saitama-ken, JP;

Takahiro Kawano, Kanagawa-ken, JP;

Yuji Kato, Hyogo-ken, JP;

Inventors:

Yusuke Kawaguchi, Kanagawa-ken, JP;

Kazuya Nakayama, Kanagawa-ken, JP;

Tsuyoshi Ohta, Kanagawa-ken, JP;

Takeshi Uchihara, Saitama-ken, JP;

Takahiro Kawano, Kanagawa-ken, JP;

Yuji Kato, Hyogo-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.


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