Cmos process with optimized pmos and nmos transistor devices

Abstract

A semiconductor process and apparatus includes forming NMOS and PMOS transistors () with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer () in a PMOS device area () to form a relaxed semiconductor layer (), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer () prior to forming the NMOS and PMOS gate structures () overlying the channel regions, and then depositing a contact etch stop layer (-) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions () may also be formed adjacent to the PMOS gate structure () to provide an additional uni-axial stress to the bi-axially stressed channel region.