The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
Jan. 07, 2010
Masaaki Hatano, Yokohama, JP;
Motoya Okazaki, San Jose, CA (US);
Junichi Wada, Yokohama, JP;
Takeshi Nishioka, Yokohama, JP;
Hisashi Kaneko, Fujisawa, JP;
Takeshi Fujimaki, Yokohama, JP;
Kazuyuki Higashi, Yokohama, JP;
Kenji Yoshida, Yokohama, JP;
Noriaki Matsunaga, Chigasaki, JP;
Masaaki Hatano, Yokohama, JP;
Motoya Okazaki, San Jose, CA (US);
Junichi Wada, Yokohama, JP;
Takeshi Nishioka, Yokohama, JP;
Hisashi Kaneko, Fujisawa, JP;
Takeshi Fujimaki, Yokohama, JP;
Kazuyuki Higashi, Yokohama, JP;
Kenji Yoshida, Yokohama, JP;
Noriaki Matsunaga, Chigasaki, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.