The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2011

Filed:

Jun. 30, 2008
Applicants:

Tejas Krishnamohan, Palo Alto, CA (US);

Krishna Parat, Palo Alto, CA (US);

Kyu Min, San Jose, CA (US);

Srivardhan Gowda, Boise, ID (US);

Thomas M. Graettinger, Boise, ID (US);

Nirmal Ramaswamy, Boise, ID (US);

Inventors:

Tejas Krishnamohan, Palo Alto, CA (US);

Krishna Parat, Palo Alto, CA (US);

Kyu Min, San Jose, CA (US);

Srivardhan Gowda, Boise, ID (US);

Thomas M. Graettinger, Boise, ID (US);

Nirmal Ramaswamy, Boise, ID (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.


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