Fast, low power formatter for automatic test system

Abstract

Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set an reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.