The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2011

Filed:

Jul. 26, 2007
Applicants:

Shinji Aono, Chiyoda-ku, JP;

Hideki Takahashi, Chiyoda-ku, JP;

Yoshifumi Tomomatsu, Chiyoda-ku, JP;

Junichi Moritani, Chiyoda-ku, JP;

Inventors:

Shinji Aono, Chiyoda-ku, JP;

Hideki Takahashi, Chiyoda-ku, JP;

Yoshifumi Tomomatsu, Chiyoda-ku, JP;

Junichi Moritani, Chiyoda-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
Abstract

A carrier storage layer is located in a region of a predetermined depth from a surface of an N− substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N− substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N− substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.


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