The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2011

Filed:

Apr. 16, 2008
Applicants:

Isao Yokokawa, Annaka, JP;

Hiroshi Takeno, Annaka, JP;

Nobuhiko Noto, Annaka, JP;

Inventors:

Isao Yokokawa, Annaka, JP;

Hiroshi Takeno, Annaka, JP;

Nobuhiko Noto, Annaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a psilicon single crystal wafer and a bond wafer consisting of a silicon single crystal wafer containing a dopant at a lower concentration than that in the base wafer; a step of forming a silicon oxide film on an entire surface of the base wafer based on thermal oxidation; a step of bonding the bond wafer to the base wafer through the silicon oxide film; and a step of reducing a thickness of the bond wafer to form an SOI layer, wherein a step of forming a CVD insulator film on a surface on an opposite side of a bonding surface of the base wafer is provided before the thermal oxidation step for the base wafer. As a result, it is possible to provide the method for manufacturing an SOI wafer which can easily prevent the p-type dopant contained in the base wafer from outwardly diffusing from the surface on the opposite side of the bonding surface of the base wafer due to a high-temperature heat treatment, suppress this dopant from being mixed into the SOI layer, and reduce warpage.


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