The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2011
Filed:
Jan. 07, 2010
Brian A. Winstead, Austin, TX (US);
Cheong M. Hong, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Spencer E. Williams, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Cheong M. Hong, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Spencer E. Williams, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.