The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2011
Filed:
Dec. 27, 2007
Roland Ruehl, San Carlos, CA (US);
Mathew Koshy, San Mateo, CA (US);
Jonathan Fales, South Burlington, VT (US);
Udayan Gumaste, San Jose, CA (US);
Roland Ruehl, San Carlos, CA (US);
Mathew Koshy, San Mateo, CA (US);
Jonathan Fales, South Burlington, VT (US);
Udayan Gumaste, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.