The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2011
Filed:
May. 30, 2008
Yuichi Harada, Matsumoto, JP;
Yoshihiro Ikura, Matsumoto, JP;
Yasumasa Watanabe, Matsumoto, JP;
Katsunori Ueno, Matsumoto, JP;
Yuichi Harada, Matsumoto, JP;
Yoshihiro Ikura, Matsumoto, JP;
Yasumasa Watanabe, Matsumoto, JP;
Katsunori Ueno, Matsumoto, JP;
Fuji Electric Co., Ltd., , JP;
Abstract
A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning.