The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2011
Filed:
Jun. 13, 2008
Hion-suck Baik, Cheonan-si, KR;
Jong-bong Park, Suwon-si, KR;
Jung-yun Won, Hwaseong-si, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Byung-seo Kim, Suwon-si, KR;
Ho Lee, Cheonan-si, KR;
Myung-sun Kim, Hwseong-si, KR;
Ji-hye Yi, Suwon-si, KR;
Hion-suck Baik, Cheonan-si, KR;
Jong-bong Park, Suwon-si, KR;
Jung-yun Won, Hwaseong-si, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Byung-seo Kim, Suwon-si, KR;
Ho Lee, Cheonan-si, KR;
Myung-sun Kim, Hwseong-si, KR;
Ji-hye Yi, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.