The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Jan. 15, 2009
Robert Rumsey, Saratoga, CA (US);
Richard Dolan, Pleasanton, CA (US);
Haowei Wu, San Jose, CA (US);
Micrel, Inc., San Jose, CA (US);
Abstract
A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.