The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Feb. 27, 2006
Yoshinobu Sato, Osaka, JP;
Hiroyoshi Ogura, Kyoto, JP;
Hisao Ichijo, Kyoto, JP;
Teruhisa Ikuta, Nara, JP;
Toru Terashita, Osaka, JP;
Yoshinobu Sato, Osaka, JP;
Hiroyoshi Ogura, Kyoto, JP;
Hisao Ichijo, Kyoto, JP;
Teruhisa Ikuta, Nara, JP;
Toru Terashita, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.