The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2011
Filed:
Aug. 20, 2008
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Tatsuya Harada, Tokyo, JP;
Nobuyuki Okuzawa, Tokyo, JP;
Satoru Sueki, Tokyo, JP;
Hiroshi Ikejima, Hong Kong, CN;
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Tatsuya Harada, Tokyo, JP;
Nobuyuki Okuzawa, Tokyo, JP;
Satoru Sueki, Tokyo, JP;
Hiroshi Ikejima, Hong Kong, CN;
Headway Technologies, Inc., Milpitas, CA (US);
TDK Corporation, Tokyo, JP;
SAE Magnetics (H.K.) Ltd., Hong Kong, CN;
Abstract
A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.