The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2011
Filed:
Aug. 16, 2007
Vedapuram S. Achutharaman, Saratoga, CA (US);
Wen Chang, Sunnyvale, CA (US);
Tarpan Dixit, San Francisco, CA (US);
Philip Kraus, San Jose, CA (US);
Vedapuram S. Achutharaman, Saratoga, CA (US);
Wen Chang, Sunnyvale, CA (US);
Tarpan Dixit, San Francisco, CA (US);
Philip Kraus, San Jose, CA (US);
Solyndra LLC, Fremont, CA (US);
Abstract
A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IBVIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.