The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2011

Filed:

May. 21, 2009
Applicants:

Pradeep Ramachandramurthy Yelehanka, Singapore, SG;

Denise Tan, Singapore, SG;

Chung Meng Lek, Singapore, SG;

Thomas Thiam, Singapore, SG;

Jeffrey C. Lam, Singapore, SG;

Liang-choo Hsia, Singapore, SG;

Inventors:

Pradeep Ramachandramurthy Yelehanka, Singapore, SG;

Denise Tan, Singapore, SG;

Chung Meng Lek, Singapore, SG;

Thomas Thiam, Singapore, SG;

Jeffrey C. Lam, Singapore, SG;

Liang-Choo Hsia, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.


Find Patent Forward Citations

Yelehanka, Pradeep. (2011). Method of manufacture an integrated circuit system with through silicon via (U.S. Patent No. 7960282). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7960282

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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