The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Mar. 21, 2008
SE Jun Kim, Changwon-si, KR;
Eun Seok Choi, Seongnam-si, KR;
Kyoung Hwan Park, Seoul, KR;
Hyun Seung Yoo, Icheon-si, KR;
Myung Shik Lee, Seoul, KR;
Young OK Hong, Icheon-si, KR;
Jung Ryul Ahn, Seoul, KR;
Yong Top Kim, Seoul, KR;
Kyung Pil Hwang, Seoul, KR;
Won Sic Woo, Guri-si, KR;
Jae Young Park, Icheon-si, KR;
Ki Hong Lee, Suwon-si, KR;
Ki Seon Park, Yongin-si, KR;
Moon Sig Joo, Icheon-si, KR;
Se Jun Kim, Changwon-si, KR;
Eun Seok Choi, Seongnam-si, KR;
Kyoung Hwan Park, Seoul, KR;
Hyun Seung Yoo, Icheon-si, KR;
Myung Shik Lee, Seoul, KR;
Young Ok Hong, Icheon-si, KR;
Jung Ryul Ahn, Seoul, KR;
Yong Top Kim, Seoul, KR;
Kyung Pil Hwang, Seoul, KR;
Won Sic Woo, Guri-si, KR;
Jae Young Park, Icheon-si, KR;
Ki Hong Lee, Suwon-si, KR;
Ki Seon Park, Yongin-si, KR;
Moon Sig Joo, Icheon-si, KR;
Hynix Semiconductor Inc., Icheon-si, Kyounki-do, KR;
Abstract
A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.