The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
May. 10, 2007
Michael W. Lane, Cortlandt Manor, NY (US);
Xiao HU Liu, Briarcliff Manor, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Ian D. W. Melville, Highland, NY (US);
Michael W. Lane, Cortlandt Manor, NY (US);
Xiao Hu Liu, Briarcliff Manor, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Ian D. W. Melville, Highland, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.