The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2011

Filed:

Aug. 03, 2007
Applicant:

Christian Val, St Remy les Chevreuse, FR;

Inventor:

Christian Val, St Remy les Chevreuse, FR;

Assignee:

3D Plus, , FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer () of thickness ecomprising silicon, covered on one face with electrical connection pads (), called test pads, and then with a thin electrically insulating layer () of thickness e, forming the insulating substrate provided with at least one silicon electronic component () having connection pads () connected to the test pads () through the insulating layer. The components are encapsulated in an insulating resin () of thickness e, filling the spaces between the components, then separated from one another by first grooves () with a width Land a depth Psuch that e+e<Pe+e+e, the connection pads of components () being connected to tracks () that are flush with the grooves (); This step, repeated K times, is followed by a step of stacking the K wafers, of forming metallized holes in the thickness of the stack, which are intended for connecting the dies together, and then of dicing the stack in order to obtain the n 3D modules.


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